Jiaxun Yang

Aye, here is Jiaxun Yang (杨嘉勋) aka FlyGoat!

I’m a PhD student at the Institute for Computing Systems Architecture (ICSA), School of Informatics, University of Edinburgh, where I’m fortunate to be co-supervised by Dr. Antonio Barbalace of the Systems-Nuts Group and Prof. Mahesh K. Marina of the NetSys Group. Before that, I received my BEng (Hons) in Electronics and Computer Science at Edinburgh as well. I’m a jack of all trades in systems, and my research sits on the boundary between software and hardware.

My research interests include:

• Memory tiering & disaggregation. How the operating system should manage tiered and disaggregated memory, especially in cloud data centers.
• Hardware-software co-design. Rethinking the interface between software and hardware, through OSes, compilers, ISAs and high-level synthesis.
• Open RAN & 5G systems. Building open, programmable and efficient systems for next-generation mobile networks.

Outside my research, I’m an open-source software/hardware hacker. I maintain a couple of niche subsystems in the Linux kernel and the MIPS backend in LLVM, and I’m a reviewer at QEMU. I created RyzenAdj and CSMWrap, and have contributed to numerous other projects, including but not limited to LiteX, MAME, picolibc, OpenBLAS, crosstool-NG, Open5GS and OCUDU. I also work part-time for a company building RISC processors, and I run AS48987 as my experimental network.

Away from the keyboard, I’m a licensed amateur radio operator (GM3HSO / BH5HSO) and a UK CAA PPL(A) pilot.